A memory system includes system boards, and data crossbars and address crossbars for connecting the system boards. Each of the system boards includes a central processing unit (CPU), a memory, a system controller, and a memory controller. Some memory systems include memories and memory controllers in a dual configuration provided on a system board. The memory controllers in a dual configuration on the system board are connected to memory controllers of another system board via different data crossbars. The memories in a dual configuration store the same data, thereby storing data redundantly.
During a normal operation, when memory controllers in a dual configuration receive, from another system board, a request for reading out data, the memory controllers read out data from memories connected to the respective memory controllers in response to the request. Each of the memory controllers transfers the read out data to a memory controller of the other system board via a data crossbar.
A memory system performs a degraded operation if one of data crossbars breaks down. In the degraded operation, a memory controller connected to a data crossbar that has not broken down reads out data and transfers the read out data to a memory controller of another system board. During the degraded operation, if the data read out by the memory controller connected to the data crossbar that has not broken down has an uncorrectable error, the system board that receives the transferred data is incapable of using the data (see, for example, Japanese Laid-open Patent Publication No. 09-006737, Japanese Laid-open Patent Publication No. 2006-039897, Japanese Laid-open Patent Publication No. 2008-046996).